This data can be entered into one’s favorite statistical analysis software package for verification. The LFSR_Plus.v module is verified in a test bench by writing out the pseudo-random values to a file. Sample histograms are included in the figures following. These distributions are created by altering a scalable LFSR output by clocking the output irregularly with a non-uniform clock, shifting scaled outputs into a buffer-adder-tree to effectively use the central limit theorem to create a normal distribution, and a feedback loop to further shape the distributions. The module gives the user 4 options for output distribution types, Gaussian unimodal, bimodal, uniform, and non-uniform distributions. This Verilog module uses 2 Linear Feedback Shift Registers (LFSR) with polynomials for maximal sequence length, one of which is scalable to output word size (4 to 24 bit) and one to operate as a non-uniform duty cycle clock. Writing Pseudo Random Numbers to File using a Test Bench (Verilog Test Fixture) Introduction.Sample output distributions (Histograms).Basic LFSR_Plus.v Core options and configuration.Using Central Limit Theorem and feedback to shape distribution.
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